1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor device manufacturing method.
2. Description of the Background Art
Heretofore, a semiconductor device (hereafter referred to as a super junction semiconductor device) including a super junction (SJ) structure with a drift layer as a parallel pn layer wherein n-type regions and p-type regions increased in impurity concentration are alternately disposed in a direction (a horizontal direction) parallel to a chip principal surface, is publicly known. In the super junction semiconductor device, current flows through the n-type regions of the parallel pn layer when in on-state, while a depletion layer also extends from the pn junction between the n-type regions and p-type regions of the parallel pn layer when in off-state, and the n-type regions and the p-type regions are depleted, thus bearing a breakdown voltage. Also, with the super junction semiconductor device, as it is possible to increase the impurity concentration of the drift layer, it is possible to reduce on-resistance while maintaining a high breakdown voltage.
As this kind of super junction semiconductor device, a device including a parallel pn layer wherein n-type regions and p-type regions are disposed in a plan view layout of stripes extending with the same width all over from an element active portion to a breakdown voltage structure portion, is proposed (for example, refer to JP-A-2008-294214 (Paragraph 0020 and FIGS. 1 and 2)). In JP-A-2008-294214, the breakdown voltage of the breakdown voltage structure portion is set to be higher than the breakdown voltage of the element active portion by setting the impurity concentration of the parallel pn layer in the breakdown voltage structure portion to be lower than the impurity concentration of the parallel pn layer in the element active portion. The element active portion is a region through which current flows when in on-state. An element peripheral portion encompasses the element active portion. The breakdown voltage structure portion is disposed in the element peripheral portion and is a region which relaxes the electric field on a chip front surface side and holds the breakdown voltage.
Also, as another super junction semiconductor device, a device wherein the repeated pitch of n-type regions and p-type regions of a parallel pn layer is set to be narrower in a breakdown voltage structure portion than in an element active portion, is proposed (for example, refer to JP-A-2002-280555 (Paragraph 0023 and FIG. 6), WO2013/008543 (Paragraph 0032 and FIGS. 1 and 2), and JP-A-2013-089921 (Paragraph 0023 and FIGS. 2, 3, and 5)). In JP-A-2002-280555, a parallel pn layer in which the n-type regions and the p-type regions are disposed in a plan view layout of stripes is provided in each of the element active portion and breakdown voltage structure portion. In WO2013/008543, the parallel pn layer in which the n-type regions and the p-type regions are disposed in the plan view layout of stripes is provided in the element active portion, and a parallel pn layer wherein the p-type regions are disposed in the n-type region in a plan view layout of matrix is provided in the breakdown voltage structure portion.
In JP-A-2013-089921, the n-type regions and the p-type regions are disposed in a plan view layout of stripes in each of the element active portion and breakdown voltage structure portion, and in each of corner portions (portion equivalent to the vertices of a rectangle) of the element active portion having a substantially rectangular plan view shape, the length of the n-type regions and p-type regions in a direction in which the stripes of the parallel pn layer extend is shortened in steps so as to follow the curvature of the corner portion of the element active portion. Also, as another super junction semiconductor device, a device wherein n-type regions and p-type regions of a parallel pn layer are disposed in a plan view layout of stripes, and in the vicinity of the boundary between an element active portion and a breakdown voltage structure portion, the width of the p-type regions of the parallel pn layer in the element active portion is gradually narrowed toward the outer side, is proposed (for example, refer to JP-A-2012-160752 (Paragraph 0051 and FIGS. 18 and 19)).
In JP-A-2002-280555, WO2013/008543, JP-A-2013-089921, and JP-A-2012-160752, in the element active portion and breakdown voltage structure portion, the impurity concentration of the parallel pn layer in the breakdown voltage structure portion is set to be lower than the impurity concentration of the parallel pn layer in the element active portion by changing the repeated pitch of the n-type regions and p-type regions of the parallel pn layer and the width of the p-type regions of the parallel pn layer. Therefore, the breakdown voltage of the breakdown voltage structure portion is higher than the breakdown voltage of the element active portion, in the same way as in JP-A-2008-294214.
As a method of forming the parallel pn layer, a method whereby n-type impurities are ion implanted all over each time a non-doped layer is stacked by epitaxial growth, and after p-type impurities are selectively ion implanted using a resist mask, the impurities are diffused by heat treatment, is proposed (for example, refer to JP-A-2011-192824 (Paragraph 0025 and FIGS. 1 to 4)). In JP-A-2011-192824, with the subsequent thermal diffusion step taken into account, the width of openings of the resist mask used to ion implant the p-type impurities is set to be on the order of ¼ of the width of the rest, in response to which the amount of p-type impurities implanted is set to be on the order of four times the amount of n-type impurities implanted, thereby equalizing the total impurity amount in the n-type regions to that in the p-type regions of the parallel pn layer.
As another method of forming the parallel pn layer, a method whereby after each of n-type and p-type impurities is selectively ion implanted using a different resist mask each time an n-type high resistance layer is stacked by epitaxial growth, the impurities are diffused by heat treatment, is proposed (for example, refer to JP-A-2000-040822 (Paragraphs 0032 to 0035 and FIG. 4)). In JP-A-2000-040822, n-type impurity implantation regions forming the n-type regions of the parallel pn layer and p-type impurity implantation regions forming the p-type regions are selectively formed so as to be opposed to each other in the horizontal direction, and are thermally diffused. Therefore, it is possible to increase the impurity concentration of both the n-type regions and p-type regions, and it is possible to suppress the variation in impurity concentration in the vicinity of the pn junction between regions adjacent in the horizontal direction.
However, as a result of the inventors' keenly repeated researches, it is newly revealed that the following problems arise when the parallel pn layer is formed in the element active portion and breakdown voltage structure portion by selectively ion implanting each of n-type and p-type impurities, as in JP-A-2000-040822. FIGS. 16A, 16B, 17A, and 17B are plan views showing a plan view layout of a parallel pn layer of a heretofore known super junction semiconductor device. FIGS. 16A and 17A show a plan view layout of a parallel pn layer, when completed, in the vicinity of a corner portion of a first parallel pn layer 104. FIGS. 16A and 17A show a ¼ portion of the heretofore known super junction semiconductor device. FIGS. 16B and 17B show a condition of the parallel pn layer in the process of being formed, respectively, in the rectangular frames AA and BB of FIGS. 16A and 17A. The parallel pn layer in each of the rectangular frames AA and BB is a parallel pn layer in a boundary region 100b between an element active portion 100a and a breakdown voltage structure portion 100c. An element peripheral portion 100d is configured of the boundary region 100b and breakdown voltage structure portion 100c. In FIGS. 16A, 16B, 17A, and 17B, a horizontal direction (hereafter referred to as a first direction) in which the stripes of the parallel pn layer extend is taken as y, and a horizontal direction (hereafter referred to as a second direction) perpendicular to the stripes is taken as x. Sign 101 is an n−-type semiconductor layer which is epitaxially grown to form the parallel pn layer.
As shown in FIGS. 16A and 17A, in the heretofore known super junction semiconductor device, the parallel pn layer (hereafter referred to as the first parallel pn layer) 104 of the element active portion 100a and a parallel pn layer (hereafter referred to as a second parallel pn layer) 114 of the breakdown voltage structure portion 100c both extend, and are in contact with each other, in the boundary region 100b between the element active portion 100a and the breakdown voltage structure portion 100c. As shown in FIGS. 16B and 17B, when forming the first and second parallel pn layers 104 and 114, n-type impurity implantation regions 121 forming first n-type regions 102 of the first parallel pn layer 104 and p-type impurity implantation regions 122 forming first p-type regions 103 are formed so as to extend in a first region 100e on the inner side (the element active portion 100a side) of the boundary region 100b. n-type impurity implantation regions 131 and 141 forming second n-type regions 112 and 115 of the second parallel pn layer 114 and p-type impurity implantation regions 132 and 142 forming second p-type regions 113 and 116 are formed so as to extend in a second region 100f on the outer side (the breakdown voltage structure portion 100c side) of the boundary region 100b. All the impurity implantation regions extend to the boundary between the first region 100e and the second region 100f. Sign 117 is a channel stopper region provided in the terminal region of the breakdown voltage structure portion 100c. 
As shown in FIGS. 16A and 16B, when setting the first n-type regions 102 and first p-type regions 103 of the first parallel pn layer 104 and the second n-type regions 112 and second p-type regions 113 of the second parallel pn layer 114 to identical repeated pitches P11 and P12 (P11=P12), the respective regions of the first and second parallel pn layers 104 and 114 attain a condition in which the same conductivity types of regions of the two parallel pn layers are in contact with each other. That is, the n-type impurity implantation regions 121 and 131 forming the first and second n-type regions 102 and 112, as well as the p-type impurity implantation regions 122 and 132 forming the first and second p-type regions 103 and 113, are disposed in a plan view layout of stripes continuing all over from the element active portion 100a to the breakdown voltage structure portion 100c. Therefore, the charge balance between the first and second parallel pn layers 104 and 114 is never lost in the boundary region 100b, but as the first and second parallel pn layers 104 and 114 both have the same impurity concentration, no difference in breakdown voltage occurs between the element active portion 100a and the breakdown voltage structure portion 100c. Consequently, there is the problem that electric field is likely to concentrate locally in the breakdown voltage structure portion 100c, and that the breakdown voltage of the whole element is determined by the breakdown voltage of the breakdown voltage structure portion 100c. 
Meanwhile, as shown in FIGS. 17A and 17B, when setting the repeated pitch P12 of the second n-type regions 115 and second p-type regions 116 to be narrower than the repeated pitch P11 of the first n-type regions 102 and first p-type regions 103 (P11>P12), the n-type impurity concentration or the p-type impurity concentration increases partially in the boundary region 100b. For example, in JP-A-2013-089921, in the corner portion of the first parallel pn layer 104, a portion 143, in which the length in the first direction y (hereafter referred to simply as the length) of the n-type impurity implantation regions 121 and p-type impurity implantation regions 142 of the first parallel pn layer 104 is shortened in steps, attains a condition in which an n-type impurity implantation region and a p-type impurity implantation region, which are different in the width in the second direction (hereafter referred to simply as the width), are adjacent to each other in the second direction x. For example, when the condition is attained in which the n-type impurity implantation region 121 and the p-type impurity implantation region 142 are adjacent to each other in the second direction x, as shown in FIG. 17B, the n-type impurity concentration of this portion becomes higher than the p-type impurity concentration. In this way, there is the problem that it is difficult, in the corner portion of the first parallel pn layer 104, to secure the charge balance in the boundary between the first parallel pn layer 104 and the second parallel pn layer 114, and that the breakdown voltage of the boundary region 100b drops partially. It is possible to suppress the partial drop in breakdown voltage due to a relative reduction in the impurity concentration of the first and second parallel pn layers 104 and 114, but the above problem leads to a drop in the breakdown voltage of the whole element.